Thesis
You are welcome to write a thesis at our group. We are always looking for motivated students that want to write a Bachelor’s or Master’s thesis. However, it is best if your interests align with our research and teaching topics such that we may adequately supervise you.
CISPA now has a central thesis portal for all theses. For the theses offered by our group, please visit the RootSec thesis portal.
# FAQ
How do I start a thesis?
Take a look at our thesis portal where we list all available thesis topics. If you find a topic that interests you, please follow the instructions on the portal to apply. If you have any questions, feel free to contact Michael Schwarz directly via email.
Can I bring my own topic?
Yes. We are happy to discuss your own ideas for a thesis. Please contact Michael Schwarz via email to discuss your ideas and see if they fit within our research scope.
How do I receive a topic?
Take a look at our thesis portal where we list all available thesis topics. If you find a topic that interests you, please follow the instructions on the portal to apply. If you have any questions, feel free to contact Michael Schwarz directly via email.
How does writing a thesis work?
After you have received your topic, you will also be assigned a direct supervisor (usually a PhD student). They will help you with quick and concrete questions and will also schedule meetings with you as needed. The duration of the thesis is at least 3 months for a Bachelor’s and at least 6 months for a Master’s thesis. The thesis will be written in English. Concurrently, you have to complete your respective seminar where you present your own topic (2 presentations) and attend presentations of other students. Please look at the requirements of the respective iteration of the seminar for more information. We will give you a more concrete outline for your particular topic and our expectations once you have decided on a topic.
What is the difference between a Bachelor's and a Master's thesis?
A Master’s thesis is allocated double the duration time by the university. As such, you are also expected to put in more work into the deliverables of the project. This is usually already reflected in the topic you received.
# Past Theses
# Bachelor’s Theses
- “Zero Pages Given: Abusing Zero-Page Deduplication for Side-Channel Attacks”, Simon Einzinger, 2025.
- “Reverse Engineering the Microarchitectural Hash Functions of the Stride Prefetcher on x86”, Eduard Ebert, 2025.
- “Key to the Kingdom: An Exploit Analysis of Programmable Input Devices”, Mona Schappert, 2024.
- “Implementation of Page Coloring in the Linux Kernel for x86”, Linda Müller, 2024.
- “PowerDrop - Fuzzing for Faulty Instruction Gadgets”, Maximilian Löffler, 2024.
- “Reversing the Microarchitecture with Unikernels”, Mikka Rainer, 2023.
- “RISCy Operations - Fuzzing the RISC-V ISA for Hidden Instructions”, Tim Schneider, 2023.
- “Turning Meltdown into a Side Channel”, Fabian Thomas, 2022.
- “Software-based Frequency Side-Channel Attacks on AMD Processors”, Ulysse Planta, 2022.
- “New Hardware - Old Vulnerabilities: Software-based Side-channel Attacks on RISC-V Architecture”, Jorim Bechtle, 2022.
- “A deterministic and fast approach to reverse engineer the DRAM addressing function”, Paul Krappen, 2022.
- “Zero Store Exploitation: Breaking SIKE with Zero Store Elimination”, Niklas Flentje, 2022.
- “Automated Reverse Engineering of LLC Complex Addressing”, Alaeddine Abroug, 2022.
- “Power-ups for Chromium: Facilitate Side-Channel Research”, Jonathan Busch, 2022.
- “(M)WAIT for It: Secret MONITORing using CPU Features”, Jonas Büchner, 2021.
- “Exploiting Spectre on iOS”, Lorenz Hetterich, 2021.
- “Browser-based CPU Fingerprinting”, Leon Trampert, 2021.
- “Automated Identification of Building Blocks for Microarchitectural Side Channels”, Daniel Weber, 2020.
# Master’s Theses
- “uArcheology: LARGE Studying and Preserving Microarchitectural Attack Artifacts”, Niklas Flentje, 2025.
- “Execute-Only Memory as a Security Hardening Feature on x86-64”, Tristan Hornetz, 2024.
- “SpySGX: Automatic Reversing of Secsrets from Memory Traces in SGX Enclaves”, Youheng Lü, 2023.
- “Performance Counters Rethought: Actively Mitigating Microarchitectural Side Channels”, Leonard Niemann, 2023.